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PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
s 50 MHz Operation s 1 Mbyte of Linear Address Space s Optional 48 Kbytes of ROM s 1 Kbyte of Register RAM s Register-register Architecture s Footprint and Functionally Compatible Upgrade for the 8XC196NP s 32 I/O Port Pins s 16 Prioritized Interrupt Sources s 4 External Interrupt Pins and NMI Pin s 2 Flexible 16-bit Timer/Counters with Quadrature Counting Capability s 3 Pulse-width Modulator (PWM) Outputs with High Drive Capability s Full-duplex Serial Port with Dedicated Baud-rate Generator s Peripheral Transaction Server
s Chip-select Unit -- 6 Chip-select Pins -- Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select -- Programmable Wait States (0-3) for Each Chip Select -- Programmable Bus Width (8- or 16-bit) for Each Chip Select -- Programmable Address Range for Each Chip Select s Event Processor Array (EPA) with 4 High-speed Capture/Compare Channels s Multiply and Accumulate Executes in 640 ns Using the 32-bit Hardware Accumulator s 960 ns 32/16 Unsigned Division s 100-pin SQFP or 100-pin QFP Package s Complete System Development Support s High-speed CHMOS Technology
40 MHz standard; 50 MHz is Speed Premium
The 8XC196NU is a member of Intel's 16-bit MCS(R) 96 microcontroller family. The device features 1 Mbyte of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch between multiplexed and demultiplexed operation.
COPYRIGHT (c) INTEL CORPORATION, 1997
February 1997
Order Number: 272644-004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-548-4725
CONTENTS
8XC196NU Commercial CHMOS 16-bit Microcontroller 1.0 Product Overview ................................................................................................................ 1 2.0 Nomenclature Overview ...................................................................................................... 2 3.0 Pinout .................................................................................................................................. 3 4.0 Signals .............................................................................................................................. 12 5.0 Address Map ..................................................................................................................... 19 6.0 Electrical Characteristics ................................................................................................... 20 6.1 DC Characteristics........................................................................................................ 21 6.2 AC Characteristics........................................................................................................ 23 6.2.1 Relationship of XTAL1 to CLKOUT .......................................................................23 6.2.2 Explanation of AC Symbols ...................................................................................24 6.2.3 AC Characteristics -- Multiplexed Bus Mode ........................................................25 6.2.4 AC Characteristics -- Demultiplexed Bus Mode ...................................................29 6.2.5 HOLD#, HLDA# Timings .......................................................................................34 6.2.6 AC Characteristics -- Serial Port, Synchronous Mode 0 ......................................35 6.2.7 External Clock Drive ..............................................................................................36 7.0 Thermal Characteristics .................................................................................................... 38 8.0 8XC196NU Errata ............................................................................................................ 38 9.0 Datasheet Revision History ............................................................................................... 38 Figures 1. 8XC196NU Block Diagram...................................................................................................1 2. The 8XC196NU Family Nomenclature .................................................................................2 3. 80C196NU 100-pin SQFP Package.....................................................................................3 4. 80C196NU 100-pin QFP Package .......................................................................................6 5. 83C196NU 100-pin QFP Package .......................................................................................9 6. Effect of Clock Mode on CLKOUT......................................................................................23 7. System Bus Timings, Multiplexed Bus Mode .....................................................................27 8. READY Timing, Multiplexed Bus Mode..............................................................................28 9. System Bus Timings, Demultiplexed Bus Mode.................................................................31 10. READY Timing, Demultiplexed Bus Mode .........................................................................32 11. Deferred Bus Mode Timing Diagram..................................................................................33 12. HOLD#, HLDA# Timing Diagram .......................................................................................34 13. Serial Port Waveform -- Synchronous Mode 0..................................................................35 14. External Clock Drive Waveforms........................................................................................36 15. AC Testing Output Waveforms During 5.0 Volt Testing .....................................................36 16. Float Waveforms During 5.0 Volt Testing...........................................................................37
iii
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Tables 1. Description of Product Nomenclature...................................................................................2 2. 80C196NU 100-pin SQFP Pin Assignment..........................................................................4 3. 80C196NU 100-pin SQFP Pin Assignment Arranged by Functional Categories .................5 4. 80C196NU 100-pin QFP Pin Assignment ............................................................................7 5. 80C196NU 100-pin QFP Pin Assignment Arranged by Functional Categories....................8 6. 83C196NU 100-pin QFP Pin Assignment ..........................................................................10 7. 83C196NU 100-pin QFP Pin Assignment Arranged by Functional Categories..................11 8. Signal Descriptions ............................................................................................................12 9. 8XC196NU Address Map ...................................................................................................19 10. DC Characteristics Over Specified Operating Conditions ..................................................21 11. AC Timing Symbol Definitions............................................................................................24 12. AC Characteristics the 8XC196NU Will Meet, Multiplexed Bus Mode ...............................25 13. AC Characteristics the External Memory System Must Meet, Multiplexed Bus Mode .......26 14. AC Characteristics the 8XC196NU Will Meet, Demultiplexed Bus Mode...........................29 15. AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode...30 16. HOLD#, HLDA# Timings ....................................................................................................34 17. Serial Port Timing -- Synchronous Mode 0 .......................................................................35 18. External Clock Drive...........................................................................................................36 19. Thermal Characteristics .....................................................................................................38
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
1.0
PRODUCT OVERVIEW
The 8XC196NU is a member of Intel's 16-bit MCS(R) 96 microcontroller family. The device features 1 Mbyte of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch between multiplexed and demultiplexed operation.
16 CPU 1000 Byte Register File 48 Kbytes ROM (optional)
RALU
Interrupt Controller
24 Bytes CPU SFRs
Microcode Engine
Peripheral Transaction Server 8 16
Memory Controller with Chip Select Queue
Chip Select CS5:0#
Control Signals A19:16/ EPORT3:0
A15:0 Pulse Width Modulator
Timer 1 Timer 2
Event Processor Array
Serial Port
Baud Rate Gen
AD15:0
Port 1
Port 2
Port 3
Port 4
Port 1/ EPA3:0, Timer 1, Timer 2
Port 2/ Hold Control, SIO, EXTINT1:0
Port 3/ Port 4/ EXTINT3:2 PWM2:0
A2822-02
Figure 1. 8XC196NU Block Diagram
PRELIMINARY
1
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
2.0
NOMENCLATURE OVERVIEW
X
Te
XX
Pa ck
8
X
Pr
X
XXXXX
XX
ed pe eS vic De ily am tF uc od on Pr ati ns rm tio nfo Op sI ry es mo oc Pr me mra og
Figure 2. The 8XC196NU Family Nomenclature Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Packaging Options Options no mark S SB 0 3 C 196NU no mark 50 Description Commercial operating temperature range (0C to 70C) with Intel standard burn-in. QFP SQFP Without ROM ROM CHMOS -- 40 MHz 50 MHz
mp
Program-memory Options Process Information Product Family Device Speed
ag i ng ti Op on s
atu er
a re nd
Bu -in rn
Op tio
ns
A2815-01
2
PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
3.0
PINOUT
RESET# NMI NC A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS NC PLLEN1 P3.0 / CS0# P3.1 / CS1# P3.2 / CS2# P3.3 / CS3# VSS P3.4 / CS4# P3.5 / CS5# P3.6 / EXTINT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 VCC VSS A18 / EPORT.2 A19 / EPORT.3 WR# / WRL#
SB80C196NU
View of component as mounted on PC board
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RD# BHE# / WRH# ALE INST READY RPD ONCE PLLEN2 VCC VSS A8 A9 A10 A11 A12 A13 A14 A15 NC VSS XTAL1 XTAL2 VSS VCC P2.7 / CLKOUT
P3.7 / EXTINT3 P1.0 / EPA0 VCC P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / T1CLK P1.5 / T1DIR VCC P1.6 / T2CLK VSS P1.7 / T2DIR P4.0 / PWM0 P4.1 / PWM1 P4.2 / PWM2 P4.3 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT0 P2.3 / BREQ# P2.4 / EXTINT1 P2.5 / HOLD# P2.6 / HLDA#
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A2823-03
Figure 3. 80C196NU 100-pin SQFP Package
PRELIMINARY
3
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 2. 80C196NU 100-pin SQFP Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name RESET# NMI NC A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS NC PLLEN1 CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 VSS CS4#/P3.4 CS5#/P3.5 EXTINT2/P3.6 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name EXTINT3/P3.7 EPA0/P1.0 VCC EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 T1CLK/P1.4 T1DIR/P1.5 VCC T2CLK/P1.6 VSS T2DIR/P1.7 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 P4.3 VCC VSS TXD/P2.0 RXD/P2.1 EXTINT0/P2.2 BREQ#/P2.3 EXTINT1/P2.4 HOLD#/P2.5 HLDA#/P2.6 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name CLKOUT/P2.7 VCC VSS XTAL2 XTAL1 VSS NC A15 A14 A13 A12 A11 A10 A9 A8 VSS VCC PLLEN2 ONCE RPD READY INST ALE BHE#/WRH# RD# Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name WR#/WRL# EPORT.3/A19 EPORT.2/A18 VSS VCC EPORT.1/A17 EPORT.0/A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 VSS AD8 VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
NOTE:
To be compatible with future products, tie the NC (no connection) pins as follows: Pin 57 = VSS, Pin 16 = VCC, and Pin 3 = NC.
4
PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 3. 80C196NU 100-pin SQFP Pin Assignment Arranged by Functional Categories Address & Data Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 Pin 4 5 8 9 10 11 12 13 65 64 63 62 61 60 59 58 82 81 78 77 100 99 98 97 96 95 94 93 91 89 88 87 Processor Control Name CLKOUT EXTINT0 EXTINT1 EXTINT2 EXTINT3 NMI ONCE RESET# RPD XTAL1 XTAL2 PLLEN1 PLLEN2 Pin 51 46 48 25 26 2 69 1 70 55 54 17 68 ALE BHE#/WRH# BREQ# HOLD# HLDA# INST RD# READY WR#/WRL# Bus Control & Status Name Pin 73 74 47 49 50 72 75 71 76 Address & Data (continued) Name AD12 AD13 AD14 AD15 Pin 86 85 84 83 Input/Output Name CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 CS4#/P3.4 CS5#/P3.5 EPA0/P1.0 EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 EPORT.0 EPORT.1 EPORT.2 EPORT.3 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.6 P3.7 P4.3 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 RXD/P2.1 T1CLK/P1.4 T1DIR/P1.5 T2CLK/P1.6 T2DIR/P1.7 TXD/P2.0 Pin 18 19 20 21 23 24 27 29 30 31 82 81 78 77 46 47 48 49 50 51 25 26 41 38 39 40 45 32 33 35 37 44 NC NC NC No Connection Name Pin 3 16 57 VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Power & Ground Name Pin 6 14 28 34 42 52 67 80 92 7 15 22 36 43 53 56 66 79 90
PRELIMINARY
5
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 VCC
AD0 NC RESET# NMI NC A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS PLLEN1 P3.0 / CS0# P3.1 / CS1# P3.2 / CS2# P3.3 / CS3# VSS P3.4 / CS4# P3.5 / CS5# P3.6 / EXTINT2 NC P3.7 / EXTINT3 P1.0 / EPA0 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S80C196NU
View of component as mounted on PC board
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS A18 / EPORT.2 A19 / EPORT.3 WR# / WRL# RD# BHE# / WRH# ALE INST READY RPD ONCE PLLEN2 VCC VSS A8 A9 A10 A11 A12 A13 A14 A15 VSS XTAL1 XTAL2 VSS P2.7 / CLKOUT VCC P2.6 / HLDA# P2.5 / HOLD#
P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / T1CLK P1.5 / T1DIR VCC P1.6 / T2CLK VSS P1.7 / T2DIR P4.0 / PWM0 P4.1 / PWM1 P4.2 / PWM2 P4.3 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT0 P2.3 / BREQ# P2.4 / EXTINT1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A2824-03
Figure 4. 80C196NU 100-pin QFP Package
6
PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. 80C196NU 100-pin QFP Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NOTE: AD0 NC RESET# NMI NC A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS PLLEN1 CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 VSS CS4#/P3.4 CS5#/P3.5 Name Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name EXTINT2/P3.6 NC EXTINT3/P3.7 EPA0/P1.0 VCC EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 T1CLK/P1.4 T1DIR/P1.5 VCC T2CLK/P1.6 VSS T2DIR/P1.7 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 P4.3 VCC VSS TXD/P2.0 RXD/P2.1 EXTINT0/P2.2 BREQ#/P2.3 EXTINT1/P2.4 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name HOLD#/P2.5 HLDA#/P2.6 VCC CLKOUT/P2.7 VSS XTAL2 XTAL1 VSS A15 A14 A13 A12 A11 A10 A9 A8 VSS VCC PLLEN2 ONCE RPD READY INST ALE BHE#/WRH# Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 RD# WR#/WRL# EPORT.3/A19 EPORT.2/A18 VSS VCC EPORT.1/A17 EPORT.0/A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 VSS AD8 VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 Name
To be compatible with future proliferations, tie the NC (no connect) pin as follows: Pin 2 = VSS Pin 5 = EA# on products with internal memory (VCC = internal memory, VSS = external memory) Pin 27 = VCC
PRELIMINARY
7
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 5. 80C196NU 100-pin QFP Pin Assignment Arranged by Functional Categories Address & Data Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 Pin 6 7 10 11 12 13 14 15 66 65 64 63 62 61 60 59 83 82 79 78 1 100 99 98 97 96 95 94 92 90 89 88 Processor Control Name CLKOUT EXTINT0 EXTINT1 EXTINT2 EXTINT3 NMI ONCE RESET# RPD XTAL1 XTAL2 PLLEN1 PLLEN2 Pin 54 48 50 26 28 4 70 3 71 57 56 18 69 ALE BHE#/WRH# BREQ# HOLD# HLDA# INST RD# READY WR#/WRL# Bus Control & Status Name Pin 74 75 49 51 52 73 76 72 77 Address & Data (continued) Name AD12 AD13 AD14 AD15 Pin 87 86 85 84 Input/Output Name CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 CS4#/P3.4 CS5#/P3.5 EPA0/P1.0 EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 EPORT.0 EPORT.1 EPORT.2 EPORT.3 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.6 P3.7 P4.3 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 RXD/P2.1 T1CLK/P1.4 T1DIR/P1.5 T2CLK/P1.6 T2DIR/P1.7 TXD/P2.0 Pin 19 20 21 22 24 25 29 31 32 33 83 82 79 78 48 49 50 51 52 54 26 28 43 40 41 42 47 34 35 37 39 46 NC NC NC No Connection Name Pin 2 5 27 VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Power & Ground Name Pin 8 16 30 36 44 53 68 81 93 9 17 23 38 45 55 58 67 80 91
8
PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 VCC
AD0 NC RESET# NMI EA# A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS PLLEN1 P3.0 / CS0# P3.1 / CS1# P3.2 / CS2# P3.3 / CS3# VSS P3.4 / CS4# P3.5 / CS5# P3.6 / EXTINT2 NC P3.7 / EXTINT3 P1.0 / EPA0 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S83C196NU
View of component as mounted on PC board
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS A18 / EPORT.2 A19 / EPORT.3 WR# / WRL# RD# BHE# / WRH# ALE INST READY RPD ONCE PLLEN2 VCC VSS A8 A9 A10 A11 A12 A13 A14 A15 VSS XTAL1 XTAL2 VSS P2.7 / CLKOUT VCC P2.6 / HLDA# P2.5 / HOLD#
P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / T1CLK P1.5 / T1DIR VCC P1.6 / T2CLK VSS P1.7 / T2DIR P4.0 / PWM0 P4.1 / PWM1 P4.2 / PWM2 P4.3 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT0 P2.3 / BREQ# P2.4 / EXTINT1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A3217-02
Figure 5. 83C196NU 100-pin QFP Package
PRELIMINARY
9
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. 83C196NU 100-pin QFP Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AD0 NC RESET# NMI EA# A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS PLLEN1 CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 VSS CS4#/P3.4 CS5#/P3.5 Pin 2 = VSS Pin 27 = VCC. Name Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name EXTINT2/P3.6 NC EXTINT3/P3.7 EPA0/P1.0 VCC EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 T1CLK/P1.4 T1DIR/P1.5 VCC T2CLK/P1.6 VSS T2DIR/P1.7 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 P4.3 VCC VSS TXD/P2.0 RXD/P2.1 EXTINT0/P2.2 BREQ#/P2.3 EXTINT1/P2.4 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name HOLD#/P2.5 HLDA#/P2.6 VCC CLKOUT/P2.7 VSS XTAL2 XTAL1 VSS A15 A14 A13 A12 A11 A10 A9 A8 VSS VCC PLLEN2 ONCE RPD READY INST ALE BHE#/WRH# Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 RD# WR#/WRL# EPORT.3/A19 EPORT.2/A18 VSS VCC EPORT.1/A17 EPORT.0/A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 VSS AD8 VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 Name
NOTE:
To be compatible with future proliferations, tie the NC (no connect) pins as follows:
10
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 7. 83C196NU 100-pin QFP Pin Assignment Arranged by Functional Categories Address & Data Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 Pin 6 7 10 11 12 13 14 15 66 65 64 63 62 61 60 59 83 82 79 78 1 100 99 98 97 96 95 94 92 90 89 88 Processor Control Name CLKOUT EXTINT0 EXTINT1 EXTINT2 EXTINT3 NMI ONCE RESET# RPD XTAL1 XTAL2 PLLEN1 PLLEN2 EA# Pin 54 48 50 26 28 4 70 3 71 57 56 18 69 5 ALE BHE#/WRH# BREQ# HOLD# HLDA# INST RD# READY WR#/WRL# Address & Data (continued) Name AD12 AD13 AD14 AD15 Pin 87 86 85 84 Input/Output Name CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 CS4#/P3.4 CS5#/P3.5 EPA0/P1.0 EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 EPORT.0 EPORT.1 EPORT.2 EPORT.3 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.6 P3.7 P4.3 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 RXD/P2.1 T1CLK/P1.4 T1DIR/P1.5 T2CLK/P1.6 T2DIR/P1.7 TXD/P2.0 Pin 19 20 21 22 24 25 29 31 32 33 83 82 79 78 48 49 50 51 52 54 26 28 43 40 41 42 47 34 35 37 39 46 NC NC No Connection Name Pin 2 27 VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Power & Ground Name Pin 8 16 30 36 44 53 68 81 93 9 17 23 38 45 55 58 67 80 91
Bus Control & Status Name Pin 74 75 49 51 52 73 76 72 77
PRELIMINARY
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
4.0
SIGNALS
Table 8. Signal Descriptions Name Type I/O Description System Address Bus These address lines provide address bits 0-15 during the entire external memory cycle during both multiplexed and demultiplexed bus modes. Address Lines 16-19 These address lines provide address bits 16-19 during the entire external memory cycle, supporting extended addressing of the 1 Mbyte address space. NOTE: Internally, there are 24 address bits; however, only 20 external address pins (A19:0) are implemented. The internal address space is 16 Mbytes (000000-FFFFFFH) and the external address space is 1 Mbyte (00000-FFFFFH). The device resets to FF2080H in internal memory or F2080H in external memory. A19:16 are multiplexed with EPORT.3:0. Address/Data Lines The functions of these pins depend on the bus size and mode. When a bus access is not occurring, these pins revert to their I/O port function. 16-bit Multiplexed Bus Mode: AD15:0 drive address bits 0-15 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 8-bit Multiplexed Bus Mode: AD15:8 drive address bits 8-15 during the entire bus cycle. AD7:0 drive address bits 0-7 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 16-bit Demultiplexed Mode: AD15:0 drive or receive data during the entire bus cycle. 8-bit Demultiplexed Mode: AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data that is currently on the high byte of the internal bus. Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (A19:16 and AD15:0 for a multiplexed bus; A19:0 for a demultiplexed bus). ALE differs from ADV# in that it does not remain active during the entire bus cycle. An external latch can use this signal to demultiplex the address bits 0-15 from the address/data bus in multiplexed mode.
A15:0
A19:16
I/O
AD15:0
I/O
ALE
O
12
PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Signal Descriptions (Continued) Name BHE# Type O Byte High Enable During 16-bit bus cycles, this active-low output signal is asserted for word reads and writes and high-byte reads and writes to external memory. BHE# indicates that valid data is being transferred over the upper half of the system data bus. Use BHE#, in conjunction with A0, to determine which memory byte is being transferred over the system bus: BHE# A0 Byte(s) Accessed 0 0 both bytes 0 1 high byte only 1 0 low byte only BHE# is multiplexed with WRH#.
Description
The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
BREQ#
O
Bus Request This active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. When the bus-hold protocol is enabled (WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). BREQ# is multiplexed with P2.3. Clock Output Output of the internal clock generator. The CLKOUT frequency is 1/2 the internal operating frequency (f). CLKOUT has a 50% duty cycle. CLKOUT is multiplexed with P2.7. Chip-select Lines 0-5 The active-low output CSx# is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x. If the external memory address is outside the range assigned to the six chip selects, no chip-select output is asserted and the bus configuration defaults to the CS5# values. Immediately following reset, CS0# is automatically assigned to the range FF2000-FF20FFH (F2000-F20FFH if external). CS5:0# is multiplexed with P3.5:0. External Access This active-low input signal determines whether memory accesses to special purpose and program memory partitions (FF2000-FFDFFFH) are directed to internal or external memory. These memory accesses are directed to internal memory if EA# is deasserted and to external memory if EA# is asserted. For an access to any other memory location, the value of EA# is irrelevant. EA# is not latched and can be switched dynamically during normal operating mode. Be sure to thoroughly consider the issues, such as different access times for internal and external memory, before using this dynamic switching capability. Always connect EA# to VSS when using a microcontroller that has no internal nonvolatile memory.
CLKOUT
O
CS5#:0
O
EA#
I
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Signal Descriptions (Continued) Name EPA3:0 Type I/O Description Event Processor Array (EPA) Input/Output pins These are the high-speed input/output pins for the EPA capture/compare channels. For high-speed PWM applications, the outputs of two EPA channels (either EPA0 and EPA1 or EPA2 and EPA3) can be remapped to produce a PWM waveform on a shared output pin. EPA3:0 are multiplexed with P1.3:0. Extended Addressing Port This is a standard, 4-bit, bidirectional I/O port. EPORT.3:0 are multiplexed with A19:16. External Interrupts In normal operating mode, a rising edge on EXTINTx sets the EXTINTx interrupt pending bit. EXTINTx is sampled during phase 2 (CLKOUT high). The minimum high time is one state time. In standby and powerdown modes, asserting the EXTINTx signal for at least 50 ns causes the device to resume normal operation. The interrupt need not be enabled, but the pin must be configured as a special-function input. If the EXTINTx interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the CPU executes the instruction that immediately follows the command that invoked the power-saving mode. In idle mode, asserting any enabled interrupt causes the device to resume normal operation. EXTINT0 is multiplexed with P2.2, EXTINT1 is multiplexed with P2.4, EXTINT2 is multiplexed with P3.6, and EXTINT3 is multiplexed with P3.7. Bus Hold Acknowledge This active-low output indicates that the CPU has released the bus as the result of an external device asserting HOLD#. When the bus-hold protocol is enabled (WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). HLDA# is multiplexed with P2.6. Bus Hold Request An external device uses this active-low input signal to request control of the bus. When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can function only as HOLD#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). HOLD# is multiplexed with P2.5. Instruction Fetch This active-high output signal is valid only during external memory bus cycles. When high, INST indicates that an instruction is being fetched from external memory. The signal remains high during the entire bus cycle of an external instruction fetch. INST is low for data accesses, including interrupt vector fetches and chip configuration byte reads. INST is low during internal memory fetches.
EPORT.3:0
I/O
EXTINT3:0
I
HLDA#
O
HOLD#
I
INST
O
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Signal Descriptions (Continued) Name NMI Type I Description Nonmaskable Interrupt In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for greater than one state time to guarantee that it is recognized. On-circuit Emulation Holding ONCE high during the rising edge of RESET# places the device into on-circuit emulation (ONCE) mode. This mode puts all pins into a high-impedance state, thereby isolating the device from other components in the system. The value of ONCE is latched when the RESET# pin goes inactive. While the device is in ONCE mode, you can debug the system using a clip-on emulator. To exit ONCE mode, reset the device by pulling the RESET# signal low. To prevent accidental entry into ONCE mode, connect the ONCE pin to VSS. P1.7:0 I/O Port 1 This is a standard bidirectional port that is multiplexed with individually selectable special-function signals. Port 1 is multiplexed as follows: P1.0/EPA0, P1.1/EPA1, P1.2/EPA2, P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR. P2.7:0 I/O Port 2 This is a standard bidirectional port that is multiplexed with individually selectable special-function signals. Port 2 is multiplexed as follows: P2.0/TXD, P2.1/RXD, P2.2/EXTINT0, P2.3/ BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and P2.7/CLKOUT. Port 3 This is an 8-bit, bidirectional, standard I/O port. Port 3 is multiplexed as follows: P3.0/CS0#, P3.1/CS1#, P3.2/CS2#, P3.3/ CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and P3.7/EXTINT3. Port 4 This is a 4-bit, bidirectional, standard I/O port with high-current drive capability. Port 4 is multiplexed as follows: P4.0/PWM0, P4.1/PWM1, and P4.2/PWM2. P4.3 is not multiplexed. Phase-locked Loop 1 and 2 Enable These input pins are used to enable the on-chip clock multiplier feature and select either the doubled or quadrupled clock speed as follows: PLLEN2 PLLEN1 Mode 0 1 0 1 0 0 1 1 Standard mode; clock multiplier circuitry disabled. Internal clock equals the XTAL1 input frequency. Reserved Doubled mode; clock multiplier circuitry enabled. Internal clock is twice the XTAL1 input frequency. Quadrupled mode; clock multiplier circuitry enabled. Internal clock is four times the XTAL1 input frequency.
ONCE
I
P3.7:0
I/O
P4.3:0
I/O
PLLEN2:1
I
This reserved combination causes the device to enter an unsupported test mode.
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Signal Descriptions (Continued) Name PWM2:0 Type O Description Pulse Width Modulator Outputs These are PWM output pins with high-current drive capability. The duty cycle and frequency-pulse-widths are programmable. PWM2:0 are multiplexed with P4.2:0. Read Read-signal output to external memory. RD# is asserted only during external memory reads. Ready Input This active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally. When READY is high, CPU operation continues in a normal manner with wait states inserted as programmed in the chip configuration registers or the chipselect x bus control register. READY is ignored for all internal memory accesses. Reset A level-sensitive reset input to and open-drain system reset output from the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-down transistor connected to the RESET# pin for 16 state times. In the powerdown, standby, and idle modes, asserting RESET# causes the chip to reset and return to normal operating mode. If the phase-locked loop (PLL) clock circuitry is enabled, you must hold RESET# low for at least 2 ms to allow the PLL to stabilize before the internal CPU and peripheral clocks are enabled. After a device reset, the first instruction fetch is from FF2080H (or F2080H in external memory). The program and special-purpose memory locations (FF2000-FF2FFFH) reside in external memory. Return from Powerdown Timing pin for the return-from-powerdown circuit. If your application uses powerdown mode, connect a capacitor between RPD and VSS if either of the following conditions is true: * the internal oscillator is the clock source * the phase-locked loop (PLL) circuitry is enabled (see PLLEN2:1 signal description) The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled. The capacitor is not required if your application uses powerdown mode and if both of the following conditions are true: * an external clock input is the clock source * RXD I/O the phase-locked loop circuitry is disabled If your application does not use powerdown mode, leave this pin unconnected. Receive Serial Data In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as either an input or an open-drain output for data. RXD is multiplexed with P2.1.
RD#
O
READY
I
RESET#
I/O
RPD
I
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Signal Descriptions (Continued) Name T1CLK Type I Description Timer 1 External Clock External clock for timer 1. Timer 1 increments (or decrements) on both rising and falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature counting mode. and External clock for the serial I/O baud-rate generator input (program selectable). T1CLK is multiplexed with P1.4. Timer 2 External Clock External clock for timer 2. Timer 2 increments (or decrements) on both rising and falling edges of T2CLK. Also used in conjunction with T2DIR for quadrature counting mode. T2CLK is multiplexed with P1.6. Timer 1 External Direction External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high and decrements when it is low. Also used in conjunction with T1CLK for quadrature counting mode. T1DIR is multiplexed with P1.5. Timer 2 External Direction External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. Also used in conjunction with T2CLK for quadrature counting mode. T2DIR is multiplexed with P1.7. Transmit Serial Data In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is the serial clock output. TXD is multiplexed with P2.0. Digital Supply Voltage Connect each VCC pin to the digital supply voltage. Digital Circuit Ground Connect each VSS pin to ground through the lowest possible impedance path. Write This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. WR# is multiplexed with WRL#. The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. Write High During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations. WRH# is multiplexed with BHE#. The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
T2CLK
I
T1DIR
I
T2DIR
I
TXD
O
VCC VSS WR#
PWR GND O
WRH#
O
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Table 8. Signal Descriptions (Continued) Name WRL# Type O Description Write Low During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# is multiplexed with WR#. The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator, phase-locked loop circuitry, and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1. The external clock signal must meet the VIH specification for XTAL1 (see datasheet). Inverted Output for the Crystal/Resonator Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses a external clock source instead of the on-chip oscillator.
XTAL1
I
XTAL2
O
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5.0
ADDRESS MAP
Table 9. 8XC196NU Address Map
Hex Address FF FFFFH FF E000H
Description External device (memory or I/O) connected to address/data bus
Addressing Modes Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended -- Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended, windowed direct Indirect, indexed, extended Indirect, indexed, windowed direct Direct, indirect, indexed, windowed direct Direct, indirect, indexed, windowed direct Direct, indirect, indexed, windowed direct
FF DFFFH Program memory (Note 1) FF 2080H FF 207FH FF 2000H FF 1FFFH FF 0100H FF 00FFH FF 0000H FE FFFFH 0F 0000H 0E FFFFH 01 0000H 00 FFFFH 00 E000H 00 DFFFH 00 2000H 00 1FFFH 00 1F00H 00 1EFFH 00 0400H 00 03FFH 00 0100H 00 00FFH 00 001AH 00 0019H 00 0018H 00 0017H 00 0000H Special-purpose memory (Note 1) External device (memory or I/O) connected to address/data bus Reserved for ICE (Note 2) Overlaid memory (reserved for future devices) (Note 2) External device (memory or I/O) connected to address/data bus External device (memory or I/O) connected to address/data bus External device (memory or I/O) connected to address/data bus or remapped internal ROM (determined by EA# pin) (Note 3) Internal peripheral special-function registers (SFRs) (Note 4) External device (memory or I/O) connected to address/data bus Upper register file (general-purpose register RAM) Lower register file (general-purpose register RAM) Lower register file (stack pointer) Lower register file (CPU SFRs) (Note 4)
NOTES: 1. For the 80C196NU, the program and special-purpose memory locations (FF2000-FFDFFFH) reside in external memory. For the 83C196NU, these locations can reside either in external memory or in internal ROM. 2. Locations xF0000-xF00FFH are reserved, write 0FFH to these locations. 3. For the 80C196NU, this address range (FF2080-FFDFFFH) is always external memory. For the 83C196NU, this address range is mapped into internal ROM if the REMAP bit (CCB1.2) is set and EA# is at logic 1. Otherwise, they are mapped to external memory. 4. Unless otherwise noted, write 0 to reserved SFR bits.
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6.0
ELECTRICAL CHARACTERISTICS
NOTICE: This document contains information on products in the sampling and initial production Storage Temperature ................................... -60C to +150C phases of development. The specifications are Supply Voltage with Respect to VSS............... -0.5 V to +7.0 V subject to change without notice. Verify with your Power Dissipation ........................................................... 1.5 W local Intel sales office that you have the latest datasheet before finalizing a design. OPERATING CONDITIONS* ABSOLUTE MAXIMUM RATINGS*
TA (Ambient Temperature Under Bias) ................ 0C to +70C VCC (Digital Supply Voltage) ............................. 4.5 V to 5.5 V FXTAL1 (Input frequency for VCC = 4.5 V - 5.5 V) (Note 1, 2, 3)........................................ 16 MHz to 50 MHz
NOTES: 1. This device is static and should operate below 1 Hz, but has been tested only down to 16 MHz. 2. The maximum crystal that can be used is 25 MHz. 3. The minimum XTAL1 frequency when using the PLL is 8 MHz.
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
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6.1
DC Characteristics
Table 10. DC Characteristics Over Specified Operating Conditions
Symbol ICC
Parameter VCC Supply Current
Min
Typical (Note 1) 90
Max 120
Units mA
Test Conditions XTAL1 = 50 MHz VCC = 5.5 V Device in Reset XTAL1 = 50 MHz VCC = 5.5 V VCC = 5.5 V (Note 2) VCC = 5.5 V VSS < VIN < VCC
IIDLE IPD ISTDBY ILI VIL VIH VIL1 VIH1 VIH2 VOL
Idle Mode Current Powerdown Mode Current Standby Mode Input Leakage Current (Standard Inputs) Input Low Voltage (all pins) Input High Voltage Input Low Voltage XTAL1 Input High Voltage XTAL1 Input High Voltage (Reset pin) (Note 3) Output Low Voltage (output configured as complementary) (Note 4, 5) Output High Voltage (output configured as complementary) (Note 5) VCC - 0.3 VCC - 0.7 VCC - 1.5 -0.5 0.2 VCC + 1 -0.5 0.7 VCC 0.2 VCC + 1.4
45 20 8
60 50 15 10 0.8 VCC + 0.5 0.3 VCC VCC + 0.5 VCC + 0.5 0.3 0.45 1.5
mA A mA A V V V V V V V V V V V
IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA
VOH
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For temperatures below 100C, typical is 10 A. 3. B-step only. 4. For all pins except P4.3:0, which have higher drive capability (see VOL1). 5. During normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: Group P1.7:3, P4 P2 P1.2:0, P3 6. 7. IOL (mA) 40 40 40 IOH (mA) 40 40 40 Individual P1, P2, P3 P4 IOL (mA) 10 18 IOH (mA) 10 10
For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3). Pin capacitance is not tested. This value is based on design simulations.
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 10. DC Characteristics Over Specified Operating Conditions (Continued) Symbol VOL1 Parameter Output Low Voltage on P4.x (output configured as complementary) (Note 5) Output Low Voltage in RESET on ALE, INST, and NMI Output High Voltage in RESET (Note 6) Output Low Voltage in RESET for ONCE pin Output Low Voltage on XTAL2 VCC - 0.7 0.45 0.3 0.45 1.5 VCC - 0.3 VCC - 0.7 VCC - 1.5 0.3 10 9 95 Min Typical (Note 1) Max 0.45 0.6 0.45 Units V V V Test Conditions IOL = 10 mA IOL = 15 mA IOL = 3 A
VOL2
VOH1 VOL3 VOL4
V V V V V V V V V pF k
IOH = -3 A IOL = 30 A IOL = 100 A IOL = 700 A IOL = 3 mA IOH = -100 A IOH = -700 A IOH = -3 mA
VOH2
Output High Voltage on XTAL2
VTH+ - VTH- CS RRST
Hysteresis voltage width on RESET# pin Pin Capacitance (any pin to VSS) (Note 7) RESET Pull-up Resistor
VCC = 5.5 V, VIN = 4.0 V
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For temperatures below 100C, typical is 10 A. 3. B-step only. 4. For all pins except P4.3:0, which have higher drive capability (see VOL1). 5. During normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: Group P1.7:3, P4 P2 P1.2:0, P3 6. 7. IOL (mA) 40 40 40 IOH (mA) 40 40 40 Individual P1, P2, P3 P4 IOL (mA) 10 18 IOH (mA) 10 10
For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3). Pin capacitance is not tested. This value is based on design simulations.
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6.2
6.2.1
AC Characteristics
RELATIONSHIP OF XTAL1 TO CLKOUT
TXHCH XTAL1 (12.5 MHz)
f PLLEN2:1=00
t = 80ns
CLKOUT
f PLLEN2:1=01
t = 40ns
CLKOUT
f PLLEN2:1=11 t = 20ns
CLKOUT
A3160-02
Figure 6. Effect of Clock Mode on CLKOUT
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6.2.2 EXPLANATION OF AC SYMBOLS
Each AC timing symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Table 11. AC Timing Symbol Definitions Character A B C D H HA L Q R S W X Y Character H L V X Z High Low Valid No Longer Valid Floating (low impedance) AD15:0, A19:0 BHE# CLKOUT AD15:0, AD7:0 HOLD# HLDA# ALE AD15:0, AD7:0 RD# CSx# WR#, WRL# XTAL1, READY Condition Signal(s)
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6.2.3
AC CHARACTERISTICS -- MULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 12. AC Characteristics the 8XC196NU Will Meet, Multiplexed Bus Mode Symbol FXTAL1 Parameter Frequency on XTAL1, PLL in 1x mode Frequency on XTAL1, PLL in 2x mode Frequency on XTAL1, PLL in 4x mode f Operating frequency, f = FXTAL1; PLL in 1x mode Operating frequency, f = 2FXTAL1; PLL in 2x mode Operating frequency, f = 4FXTAL1; PLL in 4x mode t TXHCH TCLCL TCHCL TAVWL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TQVWH TCHWH Period, t = 1/f XTAL1 Rising Edge to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period Address Valid to WR# Falling Edge CLKOUT Falling Edge to ALE Rising Edge ALE Falling Edge to CLKOUT Rising Edge ALE Cycle Time ALE High Period Address Valid to ALE Falling Edge Address Hold after ALE Falling Edge ALE Falling Edge to RD# Falling Edge RD# Low to CLKOUT Falling Edge RD# Low Period RD# Rising Edge to ALE Rising Edge RD# Low to Address Float ALE Falling Edge to WR# Falling Edge Data Stable to WR# Rising Edge CLKOUT High to WR# Rising Edge t - 11 t - 14 - 15 5 t - 10 2t - 25 - 10 - 15 4t t - 10 t - 14 t - 10 t - 15 - 10 t - 10 t-5 t + 15 5 20 t + 10 10 15 20 3 2t t + 15 62.5 50 ns ns ns ns ns ns ns ns (3) ns ns ns ns ns ns (3) ns (4) ns ns 16 50 MHz Min 16 8 (2) 8 (2) Max 50 (1) 25 12.5 Units MHz MHz MHz
ns (3)
ns
NOTES: 1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz can be applied with an external clock source. 2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8 MHz. The PLL cannot be run at frequencies lower than 16 MHz. 3. If wait states are used, add 2t x n, where n = number of wait states. 4. Assuming back-to-back bus cycles. 5. 8-bit bus only.
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Table 12. AC Characteristics the 8XC196NU Will Meet, Multiplexed Bus Mode (Continued) Symbol TWLWH TWHQX TWHLH TWHBX WR# Low Period Data Hold after WR# Rising Edge WR# Rising Edge to ALE Rising Edge BHE#, INST Hold after WR# Rising Edge A-step B-step AD15:8 Hold after WR# Rising Edge BHE#, INST Hold after RD# Rising Edge A-step B-step AD15:8 Hold after RD# Rising Edge A19:16, CS# Hold after WR# Rising Edge A19:16, CS# Hold after RD# Rising Edge Parameter Min t - 10 t-7 t - 14 t-4 0 t-4 t 0 t 0 0 t + 20 Max Units ns (3) ns ns ns ns (5) ns ns (5) ns ns
TWHAX TRHBX
TRHAX TWHSH TRHSH
NOTES: 1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz can be applied with an external clock source. 2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8 MHz. The PLL cannot be run at frequencies lower than 16 MHz. 3. If wait states are used, add 2t x n, where n = number of wait states. 4. Assuming back-to-back bus cycles. 5. 8-bit bus only.
Table 13. AC Characteristics the External Memory System Must Meet, Multiplexed Bus Mode Symbol TAVDV TRLDV TSLDV TCHDV TRHDZ TRXDX TAVYV TCLYX TYLYH Parameter AD15:0 Valid to Input Data Valid RD# Active to Input Data Valid Chip Select Low to Data Valid CLKOUT High to Input Data Valid End of RD# to Input Data Float Data Hold after RD# Inactive AD15:0 Valid to READY Setup READY Hold after CLKOUT Low Non-READY Time 0 0 2t - 38 2t - 36 Min Max 3t - 32 t - 22 4t - 32 2t - 25 t-5 Units ns (1) ns (1) ns (1) ns ns ns ns (2) ns (3) ns
No Upper Limit
NOTES: 1. If wait states are used, add 2t x n, where n = number of wait states. 2. When forcing wait states using the BUSCON register, add 2t x n. 3. Exceeding the maximum specification causes additional wait states.
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.3.1
System Bus Timings, Multiplexed Bus
TCLCL t TCLLH TCHDV TRLCL TCHCL
CLKOUT
TLLCH TLHLH TLLRL TRHLH TLHLL
ALE
TRLRH TRLAZ TRHDZ
RD#
TAVLL TRLDV TLLAX TAVDV Data In TLLWL TWLWH TCHWH TWHLH TWHQX
AD15:0 (read)
Address Out
WR#
TQVWH
AD15:0 (write) BHE#, INST BHE#, INST AD15:8 A19:16 CSx#
Address Out
Data Out
Address Out TWHBX, TRHBX
Valid
Valid TWHAX, TRHAX High Address Out TWHSH, TRHSH Extended Address Out
Valid
80C196NU A-1 Step 80C196NU B Step and 83C196NU
A4389-01
Figure 7. System Bus Timings, Multiplexed Bus Mode
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.3.2 READY Timing, Multiplexed Bus
TCLYX (max)
CLKOUT
TAVYV TCLYX (min)
READY
TLHLH + 2t
ALE
TRLRH + 2t
RD#
TRLDV + 2t
AD15:0 (read) WR# AD15:0 (write) BHE#, INST BHE#, INST A19:0 CSx#
TAVDV + 2t Data In TWLWH + 2t
TQVWH + 2t Data Out
Valid
Valid
Extended Address Out
Valid
80C196NU A-1 Step 80C196NU B Step and 83C196NU
A4388-01
Figure 8. READY Timing, Multiplexed Bus Mode
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6.2.4
AC CHARACTERISTICS -- DEMULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 14. AC Characteristics the 8XC196NU Will Meet, Demultiplexed Bus Mode Symbol FXTAL1 Parameter Frequency on XTAL1, PLL in 1x mode Frequency on XTAL1, PLL in 2x mode Frequency on XTAL1, PLL in 4x mode f Operating frequency, f = FXTAL1; PLL in 1x mode Operating frequency, f = 2FXTAL1; PLL in 2x mode Operating frequency, f = 4FXTAL1; PLL in 4x mode t TAVWL TAVRL TRHRL TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TRLCL TRLRH TRHLH TWLCL TQVWH TCHWH TWLWH TWHQX Period, t = 1/f Address Valid to WR# Falling Edge Address Valid to RD# Falling Edge Read High to Next Read Low XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling Edge to ALE Rising Edge ALE Falling Edge to CLKOUT Rising Edge ALE Cycle Time ALE High Period RD# Low to CLKOUT Falling Edge RD# Low Period RD# Rising Edge to ALE Rising Edge WR# Low to CLKOUT Falling Edge Data Stable to WR# Rising Edge CLKOUT High to WR# Rising Edge WR# Low Period Data Hold after WR# Rising Edge t - 10 - 10 - 15 4t t - 10 -5 3t - 18 t-4 -8 3t - 25 - 11 3t - 18 t t + 20 10 t + 15 5 t + 10 11 20 t-8 t-8 t-5 3 2t t + 15 10 15 50 62.5 ns ns(3) ns(3) ns(3) ns ns ns ns ns ns (3,4,5) ns ns ns (4) 16 50 MHz Min 16 8 (2) 8 (2) Max 50 (1) 25 12.5 Units MHz MHz MHz
ns (3)
ns ns (4) ns ns (4) ns
NOTES: 1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz can be applied with an external clock source. 2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8 MHz. The PLL cannot be run at frequencies lower than 16 MHz. 3. For deferred bus cycle, add 2t (1 state) if CSx# changes or if the write cycle follows a read cycle. 4. If wait states are used, add 2t x n, where n = number of wait states. 5. Assuming back-to-back bus cycles.
PRELIMINARY
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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 14. AC Characteristics the 8XC196NU Will Meet, Demultiplexed Bus Mode (Continued) Symbol TWHLH TWHBX Parameter WR# Rising Edge to ALE Rising Edge BHE#, INST Hold after WR# Rising Edge A-step B-step A19:0, CSx# Hold after WR# Rising Edge BHE#, INST Hold after RD# Rising Edge A-step B-step A19:0, CSx# Hold after RD# Rising Edge Min t-5 t-5 0 0 t-5 0 0 Max t + 10 Units ns (3) ns ns ns ns
TWHAX TRHBX
TRHAX
NOTES: 1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz can be applied with an external clock source. 2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8 MHz. The PLL cannot be run at frequencies lower than 16 MHz. 3. For deferred bus cycle, add 2t (1 state) if CSx# changes or if the write cycle follows a read cycle. 4. If wait states are used, add 2t x n, where n = number of wait states. 5. Assuming back-to-back bus cycles.
Table 15. AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode Symbol TAVDV TRLDV TSLDV TCHDV TRHDZ TRXDX TAVYV TCLYX TYLYH Parameter A19:0 Valid to Input Data Valid RD# Active to Input Data Valid Chip Select Low to Data Valid CLKOUT High to Input Data Valid End of RD# to Input Data Float Data Hold after RD# Inactive A19:0 Valid to READY Setup READY Hold after CLKOUT Low Non READY Time 0 0 3t - 45 2t - 26 Min Max 4t - 25 3t - 35 4t - 25 2t - 25 t Units ns (1,2) ns (1) ns (1,2) ns ns ns ns (3) ns (4) ns
No Upper Limit
NOTES: 1. If wait states are used, add 2t x n, where n = number of wait states. 2. For deferred bus cycle, add 2t (1 state) if CSx# changes or if the write cycle follows a read cycle. 3. When forcing wait states using the BUSCON register, add 2t x n. 4. Exceeding the maximum specification causes additional wait states.
30
PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.4.1
System Bus Timings, Demultiplexed Bus
TCHCL TCLLH
TCLCL
t TCHWH
CLKOUT
TLHLH TLLCH TWHLH TRHLH TLHLL
ALE
TRHRL TRHDZ TRHAX
TAVRL
TRLRH TCHDV TRLDV TAVDV TSLDV Data In TWLCL
RD#
AD15:0 (read)
TAVWL
TWHQX TWHAX TWLWH
WR#
TQVWH
AD15:0 (write) BHE#, INST BHE#, INST A19:0 CSx#
Valid
Data Out
Valid TWHBX,TRHBX
Address Out
Valid
80C196NU A-1 Step 80C196NU B Step and 83C196NU
A4390-01
Figure 9. System Bus Timings, Demultiplexed Bus Mode
PRELIMINARY
31
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.4.2 READY Timing, Demultiplexed Bus
TCLYX (max)
CLKOUT
TAVYV TCLYX (min)
READY
TLHLH + 2t
ALE
TRLRH + 2t
RD# AD15:0 (read) WR#
TRLDV + 2t TAVDV + 2t Address Out TWLWH + 2t Data In
TQVWH + 2t
AD15:0 (write) BHE#, INST BHE#, INST
Address Out
Data Out
Valid
Valid
A19:16 CSx#
Extended Address Out
Valid
80C196NU A-1 Step 80C196NU B Step and 83C196NU
A4391-01
Figure 10. READY Timing, Demultiplexed Bus Mode
32
PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.4.3
8XC196NU Deferred Bus Timing Mode Cycle 1 is a normal 4t read cycle. Cycle 2 is a write cycle that follows a read cycle, so a 2t delay is inserted. Notice that the chip-select change at the beginning of cycle 2 did not cause a double delay (4t). The chip-select change in cycle 3, a read cycle, causes a 2t delay.
The deferred bus cycle mode (enabled by setting CCB1.5) is designed to reduce bus contention when using the 8XC196NU in demultiplexed mode with slow memories. When the deferred mode is enabled, a delay will occur (equal to 2t) in the first bus cycle following a chip-select change or the first write cycle following a read cycle. This mode will work in parallel with wait states. Refer to Figure 11 to determine which control signals are affected.
CLKOUT
TLHLH + 2t TWHLH + 2t
ALE
TRHLH + 2t TAVRL + 2t
RD#
TAVDV,TSLDV + 2t
AD15:0 (read) WR# AD15:0 (write) BHE#, INST BHE#, INST A19:0 CSx#
Valid TAVWL + 2t
Valid
Data Out
Data Out
Data Out
Address Out
Valid
Valid
80C196NU A-1 Step 80C196NU B Step and 83C196NU
A5097-01
Figure 11. Deferred Bus Mode Timing Diagram
PRELIMINARY
33
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.5 HOLD#, HLDA# TIMINGS Table 16. HOLD#, HLDA# Timings Symbol THVCH TCLHAL TCLBRL THALAZ THALBZ TCLHAH TCLBRH THAHAX THAHBV Parameter HOLD# Setup Time (To guarantee recognition at next clock) CLKOUT Low to HLDA# Low CLKOUT Low to BREQ# Low HLDA# Low to Address Float HLDA# Low to BHE#, INST, RD#, WR# Weakly Driven CLKOUT Low to HLDA# High CLKOUT Low to BREQ# High HLDA# High to Address No Longer Float HLDA# High to BHE#, INST, RD#, WR# Valid -25 -25 -20 -20 Min 65 -15 -15 15 15 33 25 15 25 Max Units ns ns ns ns ns ns ns ns ns
CLKOUT
THVCH
HOLD#
THVCH
Hold Latency
TCLHAL
HLDA#
TCLHAH
TCLBRL
BREQ#
TCLBRH
THALAZ
A19:0, AD15:0 CSx#, BHE#, INST, RD#, WR# WRL#, WRH# ALE
THAHAX THAHBV
Weakly held inactive
THALBZ
TCLLH
Start of strongly driven ALE
A2460-03
Figure 12. HOLD#, HLDA# Timing Diagram
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PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.6
AC CHARACTERISTICS -- SERIAL PORT, SYNCHRONOUS MODE 0
Table 17. Serial Port Timing -- Synchronous Mode 0 Symbol TXLXL Parameter Serial Port Clock period SP_BAUD x002H SP_BAUD = x001H (Note 1) Serial Port Clock falling edge to rising edge SP_BAUD x002H SP_BAUD = x001H (Note 1) Output data setup to clock high Output data hold after clock high Next output data valid after clock high Input data setup to clock high Input data hold after clock high Last clock high to output float 2t + 30 0 t + 30 Min 6t 4t 4t - 27 2t - 27 4t - 30 2t - 30 2t + 30 4t + 27 2t + 27 Max Units ns ns ns ns ns ns ns ns ns ns
TXLXH
TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ
NOTE: 1. The minimum baud-rate (SP_BAUD) register value for receive is x002H and the minimum baud-rate (SP_BAUD) register value for transmit is x001H.
TXLXL TXD TQVXH RXD (Out) 0 TDVXH RXD (In) Valid Valid Valid 1 2 3 TXHDX Valid Valid Valid Valid Valid 4
TXLXH
TXHQV TXHQX 5 6 TXHQZ 7
A2080-02
Figure 13. Serial Port Waveform -- Synchronous Mode 0
PRELIMINARY
35
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.7 EXTERNAL CLOCK DRIVE Table 18. External Clock Drive Symbol FXTAL1 Parameter External Input Frequency (1/TXLXL), PLL disabled External Input Frequency (1/TXLXL), PLL in 2x mode External Input Frequency (1/TXLXL), PLL in 4x mode TXTAL1 Oscillator Period (TXLXL), PLL disabled Oscillator Period (TXLXL), PLL in 2x mode Oscillator Period (TXLXL), PLL in 4x mode TXHXX TXLXX TXLXH TXHXL
Min 16 8 8 20 40 80 0.35TXTAL1 0.35TXTAL1
Max 50
Units MHz MHz MHz ns ns ns ns ns ns ns
25 12.5 62.5 125 125 0.65TXTAL1 0.65TXTAL1 10 10
High Time Low Time Rise Time Fall Time
Assumes an external clock; the maximum input frequency for an external crystal oscillator is 25 MHz.
TXHXX 0.7 VCC + 0.5 V
TXLXH 0.7 VCC + 0.5 V
XLXX
TXHXL
T
0.3 VCC - 0.5 V T
0.3 VCC - 0.5 V
XLXL
A2119-02
Figure 14. External Clock Drive Waveforms
3.5 V
2.0 V 0.8 V
Test Points
2.0 V 0.8 V
0.45 V
AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0".
A2120-02
Figure 15. AC Testing Output Waveforms During 5.0 Volt Testing
36
PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
VLOAD + 0.15 V VLOAD VLOAD - 0.15 V Timing Reference Points
VOH - 0.15 V
VOL + 0.15 V
For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH 15 mA.
A2121-01
Figure 16. Float Waveforms During 5.0 Volt Testing
PRELIMINARY
37
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
7.0
THERMAL CHARACTERISTICS
1. 2. A heading was added for Section 1.0, "Product Overview," and the remaining sections were renumbered. List of features, the 8XC196NU has four options (0-3) for programmable wait states for each chip select, not sixteen (0-15) as previously stated. The ROM SQFP (SB83C196NU) pinout and pin assignment tables have been deleted. Figure 5, package designator in diagram changed to "S" from "SB" to correctly indicate the QFP package type. Table 8, EA# signal description added. Table 8, signal descriptions for BREQ#, HLDA#, HOLD#, PLLEN2:1, and RESET# have been modified. Table 9, redesigned and footnotes reordered. Table 10, VIH2 specification added with footnote. Figure 6, corrected to state PLLEN2:1=01 (not PLLEN2:1=10). Tables 12 and 14, B-step timing added for TWHBX min and TRHBX min. Table 12, deleted notes 4 and 5, added note 2, and reordered remaining notes. Table 13, deleted notes 1, 3, and 6 and reordered remaining notes. Table 14, deleted notes 4, 5, and 6, added note 2, and reordered remaining notes. Table 15, deleted notes 1, 3, and 6 and reordered remaining notes. Tables 13 and 15, the minimum timing for TRXDX improved from 2 ns to 0 ns. Figures 7-11, updated to reflect both A- and Bstep timings on the BHE#, INST signal. Section 5.4.3, the second sentence of the first paragraph, the word "and" replaced by "or". Table 19, thermal characteristics specifications have been changed and expanded. The errata list was replaced with a reference to the specification update document.
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. The Components Quality and Reliability Handbook (order number 210997) provides quality and reliability information. Table 19. Thermal Characteristics Package Type 100-pin QFP 80C196NU 100-pin SQFP 80C196NU 100-pin QFP 83C196NU JA 55C/W 66C/W 55C/W JC 11C/W 16.5C/W 11C/W
3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
8.0
8XC196NU ERRATA
The 8XC196NU may contain design defects or errors known as errata. Characterized errata that may cause the 8XC196NU's behavior to deviate from published specifications are documented in the 8XC196NU Specification Update (272864-001). Specification updates can be obtained from your local Intel sales office or from the World Wide Web (www.intel.com).
9.0
DATASHEET REVISION HISTORY
15. 16. 17. 18. 19.
This datasheet is valid for devices with a "B" or "C" designation at the end of the topside tracking number. Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. This is the -004 version of the datasheet. The following changes were made in this version: 1. 2. 3. 4. All references to "ADVANCE INFORMATION" have been changed to "PRELIMINARY". Table note added to Tables 4 and 6. Table 15, removed note (2) attachment from TRHDZ. Table 15, specification change made to the following timings: TAVDV, TSLDV, TCLYX.
The following changes were made in the -002 version of the datasheet: 1. The input frequency on XTAL1, formerly called FOSC, is now called FXTAL1. The internal operating frequency and operating period are denoted by (f) and (t), respectively. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz can be applied with an external clock source.
2.
This is the -003 version of the datasheet. The following changes were made in this version:
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PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
3. 4.
The minimum frequency input with PLL in 4x mode has changed from 4 MHz to 8MHz. The AC characteristics tables have been divided into the following: the timing specifications met by the device, and the timing specifications that must be met by the external memory system. Electrical characteristics notes #2 and #3 added to section 3.0. Maximum IOL and IOH specifications added to the DC characteristics tables. AC timings TAVWL and TSLDV added to the AC characteristics-multiplexed bus mode tables. Figure 7 added, and figures 8-12 have been revised. Thermal characteristics for the 100-pin SQFP package have been added in section 1.0.
11. Several AC timing specifications have changed.
5. 6. 7. 8. 9.
10. Specifications for the 83C196NU have been added.
PRELIMINARY
39

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